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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad624 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 precision instrumentation amplifier product description the ad624 is a high precision, low noise, instrumentation amplifier designed primarily for use with low level transducers, including load cells, strain gauges and pressure transducers. an outstanding combination of low noise, high gain accuracy, low gain temperature coefficient and high linearity make the ad624 ideal for use in high resolution data acquisition systems. the ad624c has an input offset voltage drift of less than 0.25 v/ c, output offset voltage drift of less than 10 v/ c, cmrr above 80 db at unity gain (130 db at g = 500) and a maximum nonlinearity of 0.001% at g = 1. in addition to these outstanding dc specifications, the ad624 exhibits superior ac performance as well. a 25 mhz gain bandwidth product, 5 v/ s slew rate and 15 s settling time permit the use of the ad624 in high speed data acquisition applications. the ad624 does not need any external components for pre- trimmed gains of 1, 100, 200, 500 and 1000. additional gains such as 250 and 333 can be programmed within one percent accuracy with external jumpers. a single external resistor can also be used to set the 624s gain to any value in the range of 1 to 10,000. product highlights 1. the ad624 offers outstanding noise performance. input noise is typically less than 4 nv/ hz at 1 khz. 2. the ad624 is a functionally complete instrumentation am- plifier. pin programmable gains of 1, 100, 200, 500 and 1000 are provided on the chip. other gains are achieved through the use of a single external resistor. 3. the offset voltage, offset voltage drift, gain accuracy and gain temperature coefficients are guaranteed for all pretrimmed gains. 4. the ad624 provides totally independent input and output offset nulling terminals for high precision applications. this minimizes the effect of offset voltage in gain ranging applications. 5. a sense terminal is provided to enable the user to minimize the errors induced through long leads. a reference terminal is also provided to permit level shifting at the output. features low noise: 0.2 v p-p 0.1 hz to 10 hz low gain tc: 5 ppm max (g = 1) low nonlinearity: 0.001% max (g = 1 to 200) high cmrr: 130 db min (g = 500 to 1000) low input offset voltage: 25 v, max low input offset voltage drift: 0.25 v/ c max gain bandwidth product: 25 mhz pin programmable gains of 1, 100, 200, 500, 1000 no external components required internally compensated functional block diagram 225.3 124 4445.7 80.2 50 v b 50 20k 10k 10k 10k ad624 ?nput g = 100 g = 200 g = 500 rg 1 rg 2 +input sense output ref 20k 10k
rev. c C2C ad624?pecifications model ad624a ad624b ad624c ad624s min typ max min typ max min typ max min typ max units gain gain equation (external resistor gain programming) 40, 000 r g + 1 ? ? ? ? ? ? 20% 40, 000 r g + 1 ? ? ? ? ? ? 20% 40, 000 r g + 1 ? ? ? ? ? ? 20% 40, 000 r g + 1 ? ? ? ? ? ? 20% gain range (pin programmable) 1 to 1000 1 to 1000 1 to 1000 1 to 1000 gain error g = 1 0.05 0.03 0.02 0.05 % g = 100 0.25 0.15 0.1 0.25 % g = 200, 500 0.5 0.35 0.25 0.5 % nonlinearity g = 1 0.005 0.003 0.001 0.005 % g = 100, 200 0.005 0.003 0.001 0.005 % g = 500 0.005 0.005 0.005 0.005 % gain vs. temperature g = 1 5 5 5 5 ppm/ c g = 100, 200 10 10 10 10 ppm/ c g = 500 25 15 15 15 ppm/ c voltage offset (may be nulled) input offset voltage 200 75 25 75 v vs. temperature 2 0.5 0.25 2.0 v/ c output offset voltage 5323 mv vs. temperature 50 25 10 50 v/ c offset referred to the input vs. supply g = 1 70 75 80 75 db g = 100, 200 95 105 110 105 db g = 500 100 110 115 110 db input current input bias current 50 25 15 50 na vs. temperature 50 50 50 50 pa/ c input offset current 35 15 10 35 na vs. temperature 20 20 20 20 pa/ c input input impedance differential resistance 10 9 10 9 10 9 10 9 ? differential capacitance 10 10 10 10 pf common-mode resistance 10 9 10 9 10 9 10 9 ? common-mode capacitance 10 10 10 10 pf input voltage range 1 max differ. input linear (v dl ) 10 10 10 10 v max common-mode linear (v cm ) 12 v ? g 2 v d ? ? ? ? ? ? 12 v ? g 2 v d ? ? ? ? ? ? 12 v ? g 2 v d ? ? ? ? ? ? 12 v ? g 2 v d ? ? ? ? ? ? v common-mode rejection dc to 60 hz with 1 k ? source imbalance g = 1 70 75 80 70 db g = 100, 200 100 105 110 100 db g = 500 110 120 130 110 db output rating v out , r l = 2 k ? 10 10 10 10 v dynamic response small signal C 3 db g = 1 1111mhz g = 100 150 150 150 150 khz g = 200 100 100 100 100 khz g = 500 50 50 50 50 khz g = 1000 25 25 25 25 khz slew rate 5.0 5.0 5.0 5.0 v/ s settling time to 0.01%, 20 v step g = 1 to 200 15 15 15 15 s g = 500 35 35 35 35 s g = 1000 75 75 75 75 s noise voltage noise, 1 khz r.t.i. 4 4 4 4 nv/ hz r.t.o. 75 75 75 75 nv/ hz r.t.i., 0.1 hz to 10 hz g = 1 10101010 v p-p g = 100 0.3 0.3 0.3 0.3 v p-p g = 200, 500, 1000 0.2 0.2 0.2 0.2 v p-p current noise 0.1 hz to 10 hz 60 60 60 60 pa p-p sense input r in 8 10 12 8 10 12 8 10 12 8 10 12 k ? i in 30 30 30 30 a voltage range 10 10 10 10 v gain to output 1 1 1 1 % (@ v s = 15 v, r l = 2 k and t a = +25 c, unless otherwise noted)
rev. c C3C ad624 model ad624a ad624b ad624c ad624s min typ max min typ max min typ max min typ max units reference input r in 16 20 24 16 20 24 16 20 24 16 20 24 k ? i in 30 30 30 30 a voltage range 10 10 10 10 v gain to output 1 1 1 1 % temperature range specified performance C 25 +85 C 25 +85 C 25 +85 C 55 +125 c storage C 65 +150 C 65 +150 C 65 +150 C 65 +150 c power supply power supply range 6 15 18 6 15 18 6 15 18 6 15 18 v quiescent current 3.5 5 3.5 5 3.5 5 3.5 5 ma notes 1 v dl is the maximum differential input voltage at g = 1 for specified nonlinearity, v dl at other gains = 10 v/g. v d = actual differential input voltage. 1 example: g = 10, v d = 0.50. v cm = 12 v C (10/2 0.50 v) = 9.5 v. specifications subject to change without notice. specifications shown in boldface are tested on all production unit at final electrical test. results from those tests are used to calculate outgoing quality le vels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation . . . . . . . . . . . . . . . . . . . . . 420 mw input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . indefinite storage temperature range . . . . . . . . . . . . . C 65 c to +150 c operating temperature range ad624a/b/c . . . . . . . . . . . . . . . . . . . . . . . C 25 c to +85 c ad624s . . . . . . . . . . . . . . . . . . . . . . . . . . . C 55 c to +125 c lead temperature (soldering, 60 secs) . . . . . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. connection diagram input +input rg 1 output null input null ref v s g = 200 g = 500 sense rg 2 input null output null g = 100 +v s output 1 2 5 6 7 3 4 8 16 15 12 11 10 14 13 9 top view (not to scale) ad624 short to rg 2 for desired gain for gains of 1000 short rg 1 to pin 12 and pins 11 and 13 to rg 2 metalization photograph contact factory for latest dimensions dimensions shown in inches and (mm). ordering guide temperature package package model range description option ad624ad C 25 c to +85 c 16-lead ceramic dip d-16 ad624bd C 25 c to +85 c 16-lead ceramic dip d-16 ad624cd C 25 c to +85 c 16-lead ceramic dip d-16 ad624sd C 55 c to +125 c 16-lead ceramic dip d-16 ad624sd/883b* C 55 c to +125 c 16-lead ceramic dip d-16 ad624achips C 25 c to +85 cdie ad624schips C 25 c to +85 cdie *see analog devices military data sheet for 883b specifications.
rev. c ad624?ypical characteristics 20 0 0 20 15 5 5 10 15 10 supply voltage v input voltage range v +25 c figure 1. input voltage range vs. supply voltage, g = 1 8.0 0 0 20 6.0 2.0 5 4.0 15 10 supply voltage v amplifier quiescent current ma figure 4. quiescent current vs. supply voltage 16 0 20 4 2 5 0 8 6 10 12 14 15 10 input voltage v input bias current na figure 7. input bias current vs. cmv 20 0 0 20 15 5 5 10 15 10 supply voltage v output voltage swing v figure 2. output voltage swing vs. supply voltage 16 0 20 4 2 5 0 8 6 10 12 14 15 10 supply voltage v input bias current na figure 5. input bias current vs. supply voltage 1 7 8.0 5 6 1.0 0 3 4 2 1 0 7.0 6.0 5.0 4.0 3.0 2.0 warm-up time minutes vos from final value v figure 8. offset voltage, rti, turn on drift 10 100 10k 1k 30 20 0 10 load resistance output voltage swing v p-p figure 3. output voltage swing vs. load resistance 40 40 125 20 30 75 0 10 10 20 30 75 25 25 temperature c input bias current na 125 figure 6. input bias current vs. temperature 0 500 100 10 1 1 10 10m 1m 100k 10k 1k 100 frequency hz gain v/v %5 ( %6 "*"
rev. c ad624 C5C 0 1 10 10m 1m 100k 10k 1k 100 frequency hz 100 80 60 40 cmrr db 120 140 20 g = 500 g = 1 g = 100 figure 10. cmrr vs. frequency rti, zero to 1k source imbalance 160 0 100k 40 20 10 80 60 100 120 140 10k 1k 100 frequency hz power supply rejection db g = 500 g = 100 g = 1 v s = 15v dc+ 1v p-p sinewave figure 13. negative psrr vs. frequency figure 16. low frequency voltage noise , g = 1 (system gain = 1000) 30 20 0 10 full-power response v p-p frequency hz 10k 1k 100k 1m g = 1, 100 g = 500 g = 100 g = 1000 bandwidth limited - figure 11. large signal frequency response volt nsd nv/ hz 0.1 100 1 10 1000 100k 10 1 10k 1k 100 frequency hz g = 1 g = 10 g = 100, 1000 g = 1000 figure 14. rti noise spectral density vs. gain figure 17. low frequency voltage noise, g = 1000 (system gain = 100,000) 160 0 100k 40 20 10 80 60 100 120 140 10k 1k 100 frequency hz power supply rejection db g = 500 g = 100 g = 1 v s = 15v dc+ 1v p-p sinewave figure 12. positive psrr vs. frequency 10 10k 100 1000 100k 100k 1 0.1 10k 100 10 frequency hz current noise spectral density fa/ hz figure 15. input current noise 20 8 to 8 12 to 12 0 output step v 4 to 4 4 to 4 8 to 8 12 to 12 15 10 5 settling time s 1% 1% 0.1% 0.01% 0.1% 0.01% figure 18. settling time, gain = 1
rev. c ad624 C6C figure 19. large signal pulse response and settling time, g = 1 figure 22. range signal pulse response and settling time, g = 500 20 8 to 8 12 to 12 0 output step v 4 to 4 4 to 4 8 to 8 12 to 12 15 10 5 settling time s 1% 1% 0.1% 0.01% 0.1% 0.01% figure 20. settling time gain = 100 20 8 to 8 12 to 12 0 output step v 4 to 4 4 to 4 8 to 8 12 to 12 15 10 5 settling time s 0.1% 0.1% 1% 1% 0.01% 0.01% figure 23. settling time gain = 1000 figure 21. large signal pulse response and settling time, g = 100 figure 24. large signal pulse response and settling time, g = 1000
rev. c ad624 C7C ad624 +v s v out 10k 1% 1k 10t 10k 1% rg 1 g = 100 g = 200 g = 500 rg 2 v s 200 0.1% 100k 1% 500 0.1% 1k 0.1% input 20v p-p figure 25. settling time test circuit theory of operation the ad624 is a monolithic instrumentation amplifier based on a modification of the classic three-op-amp instrumentation amplifier. monolithic construction and laser-wafer-trimming allow the tight matching and tracking of circuit components and the high level of performance that this circuit architecture is ca- pable of. a preamp section (q1 C q4) develops the programmed gain by the use of feedback concepts. feedback from the outputs of a1 and a2 forces the collector currents of q1 C q4 to be constant thereby impressing the input voltage across r g . the gain is set by choosing the value of r g from the equation, gain = 40 k r g + 1. the value of r g also sets the transconduct- ance of the input preamp stage increasing it asymptotically to the transconductance of the input transistors as r g is reduced for larger gains. this has three important advantages. first, this approach allows the circuit to achieve a very high open loop gain of 3 10 8 at a programmed gain of 1000 thus reducing gain related errors to a negligible 3 ppm. second, the gain bandwidth product which is determined by c3 or c4 and the input trans- conductance, reaches 25 mhz. third, the input voltage noise reduces to a value determined by the collector current of the input transistors for an rti noise of 4 nv/ hz at g 500. ad624 +v s 100 200 rg 2 v s 16.2k +v s 1/2 ad712 9.09k g1, 100, 200 1k 1 f g500 100 1 f 1.62m v s 1 f 16.2k 1.82k 500 1/2 ad712 figure 26. noise test circuit input considerations under input overload conditions the user will see r g + 100 ? and two diode drops (~1.2 v) between the plus and minus inputs, in either direction. if safe overload current under all conditions is assumed to be 10 ma, the maximum overload voltage is ~ 2.5 v. while the ad624 can withstand this con- tinuously, momentary overloads of 10 v will not harm the device. on the other hand the inputs should never exceed the supply voltage. the ad524 should be considered in applications that require protection from severe input overload. if this is not possible, external protection resistors can be put in series with the inputs of the ad624 to augment the internal (50 ? ) protection resis- tors. this will most seriously degrade the noise performance. for this reason the value of these resistors should be chosen to be as low as possible and still provide 10 ma of current limiting under maximum continuous overload conditions. in selecting the value of these resistors, the internal gain setting resistor and the 1.2 volt drop need to be considered. for example, to pro- tect the device from a continuous differential overload of 20 v at a gain of 100, 1.9 k ? of resistance is required. the internal gain resistor is 404 ? ; the internal protect resistor is 100 ? . there is a 1.2 v drop across d1 or d2 and the base-emitter junction of either q1 and q3 or q2 and q4 as shown in figure 27, 1400 ? of external resistance would be required (700 ? in series with each input). the rti noise in this case would be 4 ktr ext + (4 nv / hz ) 2 = 6.2 nv / hz 50 13 50 a i1 50 a c3 i2 50 a r57 20k r56 20k 500 sense +in v o ref i4 50 a 200 100 4445 80.2 124 225.3 in v s rg 1 rg 2 c4 vb a2 r52 10k r55 10k a3 r53 10k r54 10k +v s 50 q1, q3 q2, q4 a1 figure 27. simplified circuit of amplifier; gain is defined as (r56 + r57)/(r g ) + 1. for a gain of 1, r g is an open circuit. input offset and output offset voltage offset specifications are often considered a figure of merit for instrumentation amplifiers. while initial offset may be adjusted to zero, shifts in offset voltage due to temperature variations will cause errors. intelligent systems can often correct for this factor with an autozero cycle, but there are many sm all- signal high-gain applications that don t have this capability. voltage offset and offset drift each have two components; input and ou tput. input offset is that component of offset that is
rev. c ad624 C8C directly proportional to gain i.e., input offset as measured at the output at g = 100 is 100 times greater than at g = 1. output offset is independent of gain. at low gains, output offset drift is dominant, while at high gains input offset drift domi- nates. therefore, the output offset voltage drift is normally specified as drift at g = 1 (where input effects are insignificant), while input offset voltage drift is given by drift specification at a high gain (where output offset effects are negligible). all input- related numbers are referred to the input (rti) which is to say that the effect on the output is g times larger. voltage offset vs. power supply is also specified at one or more gain settings and is also rti. by separating these errors, one can evaluate the total error inde- pendent of the gain setting used. in a given gain configura- tion both errors can be combined to give a total error referred to the input (r.t.i.) or output (r.t.o.) by the following formula: total error r.t.i. = input error + (output error/gain) total error r.t.o. = (gain input error) + output error as an illustration, a typical ad624 might have a +250 v out- put offset and a C 50 v input offset. in a unity gain configura- tion, the total output offset would be 200 v or the sum of the two. at a gain of 100, the output offset would be C 4.75 mv or: +250 v + 100 ( C 50 v) = C 4.75 mv. the ad624 provides for both input and output offset adjust- ment. this optimizes nulling in very high precision applications and minimizes offset voltage effects in switched gain applica- tions. in such applications the input offset is adjusted first at the highest programmed gain, then the output offset is adjusted at g = 1. gain the ad624 includes high accuracy pretrimmed internal gain resistors. these allow for single connection program- ming of gains of 1, 100, 200 and 500. additionally, a variety of gains including a pretrimmed gain of 1000 can be achieved through series and parallel combinations of the internal resis- tors. table i shows the available gains and the appropriate pin connections and gain temperature coefficients. the gain values achieved via the combination of internal resistors are extremely useful. the temperature coefficient of the gain is dependent primarily on the mismatch of the temperature coefficients of the various internal resistors. tracking of these resistors is extremely tight resulting in the low gain tcs shown in table i. if the desired value of gain is not attainable using the inter- nal resistors, a single external resistor can be used to achieve any gain between 1 and 10,000. this resistor connected between ad624 g = 100 rg 2 v s output signal common v out 10k input rg 1 g = 200 g = 500 +input input offset null +v s figure 28. operating connections for g = 200 table i. temperature gain coefficient pin 3 (nominal) (nominal) to pin connect pins 1 C 0 ppm/ c CC 100 C 1.5 ppm/ c13 C 125 C 5 ppm/ c 13 11 to 16 137 C 5.5 ppm/ c 13 11 to 12 186.5 C 6.5 ppm/ c 13 11 to 12 to 16 200 C 3.5 ppm/ c12 C 250 C 5.5 ppm/ c 12 11 to 13 333 C 15 ppm/ c 12 11 to 16 375 C 0.5 ppm/ c 12 13 to 16 500 C 10 ppm/ c11 C 624 C 5 ppm/ c 11 13 to 16 688 C 1.5 ppm/ c 11 11 to 12; 13 to 16 831 +4 ppm/ c 11 16 to 12 1000 0 ppm/ c 11 16 to 12; 13 to 11 pins 3 and 16 programs the gain according to the formula r g = 40 k g ? 1 (see figure 29). for best results r g should be a precision resis- tor with a low temperature coefficient. an external r g affects both gain accuracy and gain drift due to the mismatch between it and the internal thin-film resistors r56 and r57. gain accuracy is determined by the tolerance of the external r g and the absolute accuracy of the internal resistors ( 20%). gain drift is determined by the mismatch of the temperature coefficient of r g and the tem- perature coefficient of the internal resistors ( C 15 ppm/ c typ), and the temperature coefficient of the i nternal interconnections. ad624 rg 2 v s reference v out input rg 1 2.105k +input +v s or 1.5k 1k g = + 1 = 20 20% 40.000 2.105 figure 29. operating connections for g = 20 the ad624 may also be configured to provide gain in the out- put stage. figure 30 shows an h pad attenuator connected to the reference and sense lines of the ad624. the values of r1, r2 and r3 should be selected to be as low as possible to mini- mize the gain variation and reduction of cmrr. varying r2 will precisely set the gain without affecting cmrr. cmrr is determined by the match of r1 and r3. ad624 g = 100 rg 2 v s v out input rg 1 g = 200 g = 500 +input +v s r l r3 6k r2 5k r1 6k (r 2 ||20k ) + r 1 + r 3 ) (r 2 ||20k ) g = (r 1 + r 2 + r 3 ) || r l 2k figure 30. gain of 2500
rev. c ad624 C9C noise the ad624 is designed to provide noise performance near the theoretical noise floor. this is an extremely important design criteria as the front end noise of an instrumentation amplifier is the ultimate limitation on the resolution of the data acquisition system it is being used in. there are two sources of noise in an instrument amplifier, the input noise, predominantly generated by the differential input stage, and the output noise, generated by the output amplifier. both of these components are present at the input (and output) of the instrumentation amplifier. at the input, the input noise will appear unaltered; the output noise will be attenuated by the closed loop gain (at the output, the output noise will be unaltered; the input noise will be ampli- fied by the closed loop gain). those two noise sources must be root sum squared to determine the total noise level expected at the input (or output). the low frequency (0.1 hz to 10 hz) voltage noise due to the output stage is 10 v p-p, the contribution of the input stage is 0.2 v p-p. at a gain of 10, the rti voltage noise would be 1 v p-p, 10 g ? ? ? ? ? ? 2 + 0. 2 () 2 . the rto voltage noise would be 10.2 v p-p, 10 2 + 0. 2 g () () 2 . these calculations hold for applications using either internal or external gain resistors. input bias currents input bias currents are those currents necessary to bias the input transistors of a dc amplifier. bias currents are an additional source of input error and must be considered in a total error budget. the bias currents when multiplied by the source resis- tance imbalance appear as an additional offset voltage. (what is of concern in calculating bias current errors is the change in bias current with respect to signal voltage and temperature.) input offset current is the difference between the two input bias cur- rents. the effect of offset current is an input offset voltage whose magnitude is the offset current times the source resistance. ad624 v s +v s load to power supply ground a. transformer coupled ad624 v s +v s load to power supply ground b. thermocouple ad624 v s +v s load to power supply ground =
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- although instrumentation amplifiers have differential inputs, there must be a return path for the bias currents. if this is not provided, those currents will charge stray capacitances, causing the output to drift uncontrollably or to saturate. therefore, when amplifying floating input sources such as transformers and thermocouples, as well as ac-coupled sources, there must still be a dc path from each input to ground, (see figure 31). common-mode rejection common-mode rejection is a measure of the change in output voltage when both inputs are changed by equal amounts. these specifications are usually given for a full-range input voltage change and a specified source imbalance. common-mode rejection ratio (cmrr) is a ratio expression while common- mode rejection (cmr) is the logarithm of that ratio. for example, a cmrr of 10,000 corresponds to a cmr of 80 db. in an instrumentation amplifier, ac common-mode rejection is only as good as the differential phase shift. degradation of ac common-mode rejection is caused by unequal drops across differing track resistances and a differential phase shift due to varied stray capacitances or cable capacitances. in many appli- cations shielded cables are used to minimize noise. this tech- nique can create common-mode rejection errors unless the shield is properly driven. figures 32 and 33 shows active data guards which are configured to improve ac common-mode rejection by bootstrapping the capacitances of the input cabling, thus minimizing differential phase shift. ad624 rg 2 v s reference v out input +input +v s g = 200 ad711 100 figure 32. shield driver, g 100 ad624 rg 1 v s reference v out input +input +v s v s ad712 100 100 rg 2 %$$ '
rev. c ad624 C10C grounding many data-acquisition components have two or more ground pins which are not connected together within the device. these grounds must be tied together at one point, usually at the sys- tem power supply ground. ideally, a single solid ground would be desirable. however, since current flows through the ground wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point and the data acqui- sition components. separate ground returns should be provided to minimize the current flow in the path from the most sensitive points to the system ground point. in this way supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measure- ment errors (see figure 34). output reference analog ground* *if independent, otherwise return amplifier reference to mecca at analog p.s. common signal ground ad574a digital data output + 1 f 0.1 f 1 f 1 f dig com 0.1 f 0.1 f 0.1 f ad624 sample and hold ad583 analog p.s. +15v c 15v +5v digital p.s. c figure 34. basic grounding practice since the output voltage is developed with respect to the poten- tial on the reference terminal an instrumentation amplifier can solve many grounding problems. sense terminal the sense terminal is the feedback point for the instrument amplifier s output amplifier. normally it is connected to the instrument amplifier output. if heavy load currents are to be drawn through long leads, voltage drops due to current flowing through lead resistance can cause errors. the sense terminal can be wired to the instrument amplifier at the load thus putting the ixr drops inside the loop and virtually eliminating this error source. ad624 v+ output current booster v v in + v in x1 r l (ref) (sense) figure 35. ad624 instrumentation amplifier with output current booster typically, ic instrumentation amplifiers are rated for a full 10 volt output swing into 2 k ? . in some applications, how- ever, the need exists to drive more current into heavier loads. figure 35 shows how a current booster may be connected inside the loop of an instrumentation amplifier to provide the required current without significantly degrading overall perfor- mance. the effects of nonlinearities, offset and gain inaccuracies of the buffer are reduced by the loop gain of the ia output amplifier. offset drift of the buffer is similarly reduced. reference terminal the reference terminal may be used to offset the output by up to 10 v. this is useful when the load is floating or does not share a ground with the rest of the system. it also provides a direct means of injecting a precise offset. it must be remem- bered that the total output swing is 10 volts, from ground, to be shared between signal and reference offset. ad624 v in + v in ref sense load ad711 v s +v s v offset figure 36. use of reference terminal to provide output offset when the ia is of the three-amplifier configuration it is neces- sary that nearly zero impedance be presented to the reference terminal. any significant resistance, including those caused by pc layouts or other connection techniques, which appears between the reference pin and ground will increase the gain of the noninverting signal path, thereby upsetting the common- mode rejection of the ia. inadvertent thermocouple connections created in the sense and reference lines should also be avoided as they will directly affect the output offset voltage and output offset voltage drift. in the ad624 a reference source resistance will unbalance the cmr trim by the ratio of 10 k ? /r ref . for example, if the refer- ence source impedance is 1 ? , cmr will be reduced to 80 db (10 k ? /1 ? = 80 db). an operational amplifier may be used to provide that low impedance reference point as shown in figure 36. the input offset voltage characteristics of that amplifier will add directly to the output offset voltage performance of the instrumentation amplifier. an instrumentation amplifier can be turned into a voltage-to- current converter by taking advantage of the sense and reference terminals as shown in figure 37. ad624 +input ref r 1 +v x sense load ad711 a2 i l input 40.000 r g 1 + i l = = v x r 1 v in r 1 figure 37. voltage-to-current converter
rev. c ad624 C11C by establishing a reference at the low side of a current setting resistor, an output current may be defined as a function of input voltage, gain and the value of that resistor. since only a small current is demanded at the input of the buffer amplifier a2, the forced current i l will largely flow through the load. offset and drift specifications of a2 must be added to the output offset and drift specifications of the ia. programmable gain figure 38 shows the ad624 being used as a software program- mable gain amplifier. gain switching can be accomplished with mechanical switches such as dip switches or reed relays. it should be noted that the on resistance of the switch in series with the internal gain resistor becomes part of the gain equation and will have an effect on gain accuracy. a significant advantage in using the internal gain resistors in a programmable gain configuration is the minimization of thermo- couple signals which are often present in multiplexed data acquisition systems. if the full performance of the ad624 is to be achieved, the user must be extremely careful in designing and laying out his circuit to minimize the remaining thermocouple signals. the ad624 can also be connected for gain in the output stage. figure 39 shows an ad547 used as an active attenuator in the output amplifier s feedback loop. the active attenuation pre- sents a very low impedance to the feedback resistors therefore minimizing the common-mode rejection ratio degradation. another method for developing the switching scheme is to use a dac. the ad7528 dual dac which acts essentially as a pair of switched resistive attenuators having high analog linearity and symmetrical bipolar transmission is ideal in this application. the multiplying dac s advantage is that it can handle inputs of either polarity or zero without affecting the programmed gain. the circuit shown uses an ad7528 to set the gain (dac a) and to perform a fine adjustment (dac b). v dd gnd 225.3 124 4445.7 80.2 50 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 10k 20k v b 20k 10k 10k 50 v s +v s 1 f 35v in +in 10k 10k input offset null output offset null 10k to v (+input) ( input) v out 39.2k wr a4 a3 a2 a1 v ss 1k 10pf +v s 28.7k 316k 1k 1k v s ad624 ad7590 ad711 figure 39. programmable output gain 225.3 124 4445.7 80.2 50 g = 100 k1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 10k 20k v b 20k 10k 10k 50 v s +v s 1 f 35v in +in r2 10k r1 10k input offset trim output offset trim relay shields g = 200 k2 g = 500 k3 d1 d2 d3 y0 k2 k3 74ls138 decoder 7407n buffer driver a b y1 y2 inputs gain range +5v 10 f c1 c2 k1 k3 = thermosen dm2c 4.5v coil d1 d3 = in4148 analog common gain table a b gain 0 0 100 0 1 500 1 0 200 11 1 logic common k1 out 10k +5v ad624 nc figure 38. gain programmable amplifier
rev. c ad624 C12C 225.3 124 4445.7 80.2 50 v b 50 20k 10k 10k 10k ad624 g = 100 g = 200 g = 500 rg 1 rg 2 input (+input) v out 20k 10k +input ( input) ad7528 1/2 ad712 256:1 data inputs cs wr dac a /dac b db0 db7 +v s dac a dac b 1/2 ad712 figure 40. programmable output gain using a dac autozero circuits in many applications it is necessary to provide very accurate data in high gain configurations. at room temperature the offset effects can be nulled by the use of offset trimpots. over the operating temperature range, however, offset nulling becomes a problem. the circuit of figure 41 shows a cmos dac operat- ing in the bipolar mode and connected to the reference terminal to provide software controllable offset adjustments. ad624 v s +v s v out g = 100 g = 200 g = 500 rg 1 rg 2 +input input data inputs cs wr msb lsb +v s ad7524 c1 out1 out2 1/2 ad712 r fb +v s r3 20k r4 10k r5 20k v s r6 5k v s gnd ad589 39k v ref 1/2 ad712 figure 41. software controllable offset in many applications complex software algorithms for autozero applications are not available. for these applications figure 42 provides a hardware solution. ad624 v s +v s v out rg 1 rg 2 1k 12 11 910 0.1 f low leakage ch 15 16 14 13 v ss v dd gnd a1 a2 a3 a4 ad7510dikd 200 s zero pulse ad542 figure 42. autozero circuit the microprocessor controlled data acquisition system shown in figure 43 includes includes both autozero and autogain capabil- ity. by dedicating two of the differential inputs, one to ground and one to the a/d reference, the proper program calibration cycles can eliminate both initial accuracy errors and accuracy errors over temperature. the autozero cycle, in this application, converts a number that appears to be ground and then writes that same number (8 bit) to the ad624 which eliminates the zero error since its output has an inverted scale. the autogain cycle converts the a/d reference and compares it with full scale. a multiplicative correction factor is then computed and applied to subsequent readings. rg 1 rg 2 ad624 1/2 ad712 ad583 agnd v in v ref ad574a ad7507 en a1 a2 a0 address bus v ref 5k 10k 20k latch 20k 1/2 ad712 control decode ad7524 micro- processor figure 43. microprocessor controlled data acquisition system
rev. c ad624 C13C weigh scale figure 44 shows an example of how an ad624 can be used to condition the differential output voltage from a load cell. the 10% reference voltage adjustment range is required to accom- modate the 10% transducer sensitivity tolerance. the high linearity and low noise of the ad624 make it ideal for use in applications of this type particularly where it is desirable to measure small changes in weight as opposed to the absolute value. the addition of an autogain/autotare cycle will enable the system to remove offsets, gain errors, and drifts making possible true 14-bit performance. g100 g200 g500 rg 2 ad624 +input input r5 3m r6 100k zero adjust (coarse) a/d converter +10v full scale output reference sense gain = 500 r4 10k zero adjust (fine) 100 r3 10 +15v r1 30k note 2 10v 10% r2 20k r3 10k scale error adjust ad584 +10v +5v +2.5v vbg transducer see note 1 notes 1. load cell tedea model 1010 10kg. output 2mv/v 10%. 2. r1, r2 and r3 selected for ad584. output 10v 10%. +15v ad707 2n2219 r7 100k out figure 44. ad624 weigh scale application ac bridge bridge circuits which use dc excitation are often plagued by errors caused by thermocouple effects, l/f noise, dc drifts in the electronics, and line noise pickup. one way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. the ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. the low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a low- pass filter. dynamic response of the bridge must be traded off against the amount of attenuation required to adequately sup- press these residual carrier components in the selection of the filter. figure 45 is an example of an ac bridge system with the ad630 used as a synchronous demodulator. the oscilloscope photo- graph shows the results of a 0.05% bridge imbalance caused by the 1 meg resistor in parallel with one leg of the bridge. the top trace represents the bridge excitation, the upper middle trace is the amplified bridge output, the lower-middle trace is the out- put of the synchronous demodulator and the bottom trace is the filtered dc system output. this system can easily resolve a 0.5 ppm change in bridge impedance. such a change will produce a 6.3 mv change in the low-pass filtered dc output, well above the rto drifts and noise. the ac-cmrr of the ad624 decreases with the frequency of the input signal. this is due mainly to the package-pin capaci- tance associated with the ad624 s internal gain resistors. if ac-cmrr is not sufficient for a given application, it can be trimmed by using a variable capacitor connected to the amplifier s rg 2 pin as shown in figure 45. ad624c v s +v s v out g = 1000 rg 1 rg 2 10k 1khz bridge excitation 1m 1k 1k 1k 1k 4 49pf ceramic ac balance capacitor v 10k b 10k 5k 2.5k v s phase shifter ad630 modulated output signal +v s modulation input carrier input 2.5k b a comp figure 45. ac bridge 0v 0v 0v 0v bridge excitation (20v/div) (a) amplified bridge output (5v/div) (b) demodulated bridge output (5v/div) (c) filter output 2v/div) (d) 2v figure 46. ac bridge waveforms
rev. c ad624 C14C ad624c v s +v s g = 100 rg 1 rg 2 10k 350 +10v 14-bit adc 0 to 2v f.s. 350 350 350 figure 47. typical bridge application table ii. error budget analysis of ad624cd in bridge application effect on effect on absolute absolute effect ad624c accuracy accuracy on error source specifications calculation at t a = +25 c at t a = +85 c resolution gain error 0.1% 0.1% = 1000 ppm 1000 ppm 1000 ppm C gain instability 10 ppm (10 ppm/ c) (60 c) = 600 ppm _ 600 ppm C gain nonlinearity 0.001% 0.001% = 10 ppm CC 10 ppm input offset voltage 25 v, rti 25 v/20 mv = 1250 ppm 1250 ppm 1250 ppm C input offset voltage drift 0.25 v/ c( 0.25 v/ c) (60 c)= 15 v 15 v/20 mv = 750 ppm C 750 ppm C output offset voltage 1 2.0 mv 2.0 mv/20 mv = 1000 ppm 1000 ppm 1000 ppm C output offset voltage drift 1 10 v/ c( 10 v/ c) (60 c) = 600 v 600 v/20 mv = 300 ppm C 300 ppm C bias current C source 15 na ( 15 na)(5 ? ) = 0.075 v imbalance error 0.075 v/20mv = 3.75 ppm 3.75 ppm 3.75 ppm C offset current C source 10 na ( 10 na)(5 ? ) = 0.050 v imbalance error 0.050 v/20 mv = 2.5 ppm 2.5 ppm 2.5 ppm C offset current C source 10 na (10 na) (175 ? ) = 1.75 v resistance error 1.75 v/20 mv = 87.5 ppm 87.5 ppm 87.5 ppm C offset current C source 100 pa/ c (100 pa/ c) (175 ? ) (60 c) = 1 v resistance C drift 1 v/20 mv = 50 ppm C 50 ppm C common-mode rejection 115 db 115 db = 1.8 ppm 5v = 9 v 5v dc 9 v/20 mv = 444 ppm 450 ppm 450 ppm C noise, rti (0.1 hz C 10 hz) 0.22 v p-p 0.22 v p-p/20 mv = 10 ppm _ C 10 ppm total error 3793.75 ppm 5493.75 ppm 20 ppm note 1 output offset voltage and output offset voltage drift are given as rti figures. for a comprehensive study of instrumentation amplifier design and applications, refer to the instrumentation amplifier application guide , available free from analog devices. error budget analysis to illustrate how instrumentation amplifier specifications are applied, we will now examine a typical case where an ad624 is required to amplify the output of an unbalanced transducer. figure 47 shows a differential transducer, unbalanced by 5 ? , supplying a 0 to 20 mv signal to an ad624c. the output of the ia feeds a 14-bit a to d converter with a 0 to 2 volt input volt- age range. the operating temperature range is C 25 c to +85 c. therefore, the largest change in temperature ? t within the operating range is from ambient to +85 c (85 c C 25 c = 60 c.) in many applications, differential linearity and resolution are of prime importance. this would be so in cases where the absolute value of a variable is less important than changes in value. in these applications, only the irreducible errors (20 ppm = 0.002%) are significant. furthermore, if a system has an intelli- gent processor monitoring the a to d output, the addition of an autogain/autozero cycle will remove all reducible errors and may eliminate the requirement for initial calibration. this will also reduce errors to 0.002%.
rev. c ad624 C15C outline dimensions dimensions shown in inches and (mm). side-brazed solder lid ceramic dip (d-16) 16 1 8 9 0.080 (2.03) max 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.100 (2.54) bsc seating plane 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.150 (3.81) max 0.840 (21.34) max 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20)
C16C c805dC0C7/99 printed in u.s.a.

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